Voltage in phototransistor U3A is reduced in order to reduce the amount of present, and the zener diode **unity within the IRED of phototransistor U3A reduces the threshold, such that voltage goes back up. Upon disco**ion of bla** portion 22, the input at pin 1 of NAND gate U2A goes high. Pin 10 of NAND gate U2C is a brief high level allow logic with a protracted low logic obligation cycle. Without suggestions management, the output at NAND gate U1D is roughly a 50-50 responsibility cycle. Voltage management circuit 56 is **trolled by isolated primary feedback circuit 66P and isolated se**dary feedback circuit 66S, which a**plish modulation of the responsibility cycle of voltage **trol circuit 56. Isolated major feedback circuit 66P **sists of phototransistor U3B, transistor Q3, and resistors R5, R17, R14, R15 and R16, which cooperate with NAND gate U1C to perform modulation of the obligation cycle. On this method, when power switch Q6 is turned off, energy saved in transformer T transfers to se**dary aspect S, in accordance with known operation. The output from the set-reset flip flop (pin 11 of NAND gate U1D) is provided by way of resistors R10 and R11 and is present buffered by transistors Q4 and Q5 to drive power swap Q6.

The output of NAND gate U1D is related by resistors R10 and R11 to transistors Q4 and Q5. Pin 2 of NAND gate U2A is excessive due to the charge from capacitor C15, which out**es in the output of NAND gate U2A going low. Pin 12 of NAND gate U2D offers an output logic excessive at pin 1, in order to allow the fundamental frequency oscillator (U1A) and to disable the high frequency override oscillator **work. This capabilities to disable the excessive frequency override oscillator **work by grounding pin 12 of NAND gate U2D. Simultaneously, pin 2 of NAND gate U2A is pulled low, to allow the output pin eleven of NAND gate U1D. The output from NAND gate U1A is provided to a set-reset flip flop by way of NAND gate U1B, which acts as an i**er. The set-reset flip flop is a cross coupled flip flop made up of NAND gates U1B and U1C.

NAND gates U1A and U1B, that are 180